1. Field of the Invention
The present invention relates to a method for producing a semiconductor article for forming semiconductor devices such as integrated circuits, semiconductor lasers, and light emitting diodes, and more particularly to a semiconductor article production method including a step of transferring a semiconductor layer formed on a substrate to the surface of another substrate.
2. Related Background Art
The term "semiconductor article" is used herein to refer to a semiconductor wafer, a semiconductor substrate, a semiconductor substrate material, a semiconductor device, and the like. Not only those having semiconductor devices formed in their semiconductor regions, but also those which are prepared before device fabrication and have no devices are included in what this term implies.
Among such various semiconductor articles, some semiconductor articles include a semiconductor layer on an insulating material. Formation of a monocrystalline silicon (Si) semiconductor layer on an insulating material has been widely known as the silicon on insulator (SOI) technology. Those devices utilizing the SOI structure exhibit a large number of advantages which cannot be achieved by devices made simply on bulk silicon substrates, for preparation of the conventional silicon integrated circuits. Therefore, many investigations have been made. More specifically, by utilizing the SOI structure, the following advantages can be obtained:
1. Dielectric isolation can be easily made to enable high degree of integration;
2. Radiation hardness is excellent;
3. Stray capacitance can be reduced to attain high-speed operation of devices;
4. Well formation step can be omitted;
5. Latch-up can be prevented; and
6. Fully depleted field effect transistors can be achieved by thin film formation.
In order to realize the many advantages in device characteristics as mentioned above, studies have been made about the method for forming the SOI structure for some 10 years.
For example, one typical technology is SOS (silicon on sapphire) structure by heteroepitaxy of silicon on a monocrystalline sapphire substrate by CVD (chemical vapor deposition) method. Although this has been successful to some extent as the most mature SOI technique, there are still many problems to be solved to apply this technology in wide applications. For examples, there area large amount of crystal defects because of lattice mismatching at the interface between the silicon layer and the sapphire substrate. Another problem is introduction of aluminum from the sapphire substrate into the silicon layer. Furthermore, the most significant problems are the high cost of the substrate and delay in availability of large size of substrate wafers. In relatively recent years, it has been attempted to realize the SOI structure without use of a sapphire substrate. Such attempts may be classified into the following two methods:
(1) After surface oxidation of a monocrystalline silicon substrate, a window is formed to partially expose the silicon substrate, and epitaxial growth is carried out in the lateral direction using the exposed portion of silicon as a seed to form a monocrystalline silicon layer on SiO.sub.2 (In this case, deposition of silicon layer on SiO.sub.2 is accompanied.)
(2) By use of a monocrystalline silicon substrate itself as an active layer, SiO.sub.2 is formed therebeneath. (This method is accompanied with no deposition of silicon layer.)
As a means for realizing the above (1), there have been known the method in which a monocrystalline silicon layer is formed directly by gas phase lateral epitaxial growth by CVD, the method in which amorphous silicon is deposited and the resultant amorphous layer is subjected to solid phase lateral epitaxial growth by heat treatment, the method in which a deposited layer of amorphous or polycrystalline silicon is irradiated with an energy of focused beam such as electron beam, laser beam, etc., to melt and recrystallize them into a monocrystalline layer on SiO.sub.2 and the method in which a zone of amorphous layer is by a rod-shaped heater and the melted region is scanned (Zone melting recrystallization). These methods have both advantages and disadvantages, they still have many problems with respect to controllability, productivity, uniformity and quality, and none of them have been industrially applied yet to date. For example, the CVD method requires sacrifice-oxidation for flat thin film formation, while the crystallinity is poor in the solid phase growth method. On the other hand, in the beam annealing method, problems are involved in controllability of such as treatment time by converged beam scanning, overlapping of beams, focus adjustment, etc. Among these, the Zone Melting Recrystallization method is the most mature, and a relatively large scale integrated circuit has been made experimentally, but there still remain a large number of crystal defects such as point defects, line defects, plane defects (sub-boundary), etc., and no device operating with minority carriers has been realized yet.
Concerning the method using no silicon substrate as a seed for epitaxial growth according to the above method (2), the following three methods may be included.
(2-1) An oxide; film is formed on a monocrystalline silicon substrate with V-grooves as anisotropically etched on the surface, then a polycrystalline silicon layer is deposited on the oxide film to the thickness extent as the silicon substrate, and thereafter by polishing the silicon substrate from the back side, the monocrystalline silicon regions dielectrically separated by the surrounding V-grooves on the thick polycrystalline silicon layer are formed.
In this method, although crystallinity is good, there are problems with respect to controllability and productivity in the step of depositing polycrystalline silicon some hundred microns in thickness and in the step wherein the monocrystalline silicon substrate is polished from the back surface so that only the silicon active layer remains as separated.
(2-2) There is the method called SIMOX (Separation by ion-implanted oxygen) in which an SiO.sub.2 layer is formed inside a monocrystalline silicon substrate by implanting oxygen atoms into the monocrystalline silicon substrate, which is one of the most mature methods because of good matching with the Si-IC (Integrated Circuit) process.
However, for formation of the SiO.sub.2 layer, 10.sup.18 ions/cm.sup.2 or more of oxygen ions are required to be implanted, and the implantation time is too long to be good in productivity, and the wafer cost is also high. Further, from an industrial point of view, sufficiently good quality has not been achieved to fabricate a device operating with minority carriers, because many crystal defects remain.
(2-3) There is the method to form an SOI structure by dielectric isolation according to oxidation of porous silicon. In this method, islands of n-type silicon layer are formed on the surface of a p-type monocrystalline silicon substrate by way of proton ion implantation (Imai et al., J. Crystal Growth, Vol. 63, 547 (1983)), or by epitaxial growth in conjunction with patterning. Then, only the p-type silicon substrate is made porous by anodization in HF solution surrounding the silicon islands from the surface. Thus, the n-type silicon islands are dielectrically isolated by accelerated oxidation.
In this method, the possible size of separated silicon regions is limited to the range from several microns to several hundred microns. This limitation results in significant problems in device fabrication process and design. Besides, there remains large stress in the silicon islands which leads to a large number of crystal defects.
Furthermore, there are some problems in the process for removing the porous layers by chemical etching, which is inevitable for the method (2-3) described above.
In general, porosity is defined by: EQU P=(2.33-A)/2.33 (1)
This value of porosity can be changed during the anodization. The porosity can be also described by EQU P=(m1-m2)/(m1-m3) (2)
or EQU P=(m1-m2)/.rho.At (3)
wherein
m1: total weight before anodization PA1 m2: total weight after anodization PA1 m3: total weight after removal of porous silicon PA1 .rho.: density of monocrystalline silicon PA1 A: Area of porous region PA1 t: thickness of porous silicon
However, the area of the porous region cannot be accurately calculated in many cases. In this case, although the equation (2) is effective, the porous silicon must be etched to accomplish the measurement of the value m3.
On the other hand, during epitaxial growth on the porous silicon, the porous silicon is capable of relieving distortion produced during heteroepitaxial growth and suppressing the generation of defects. Also in this case, it is clear that the porosity is a very important parameter, thus measurement of the porosity is necessary and indispensable.
There are known the following methods for etching the porous silicon:
(2-3-1) The method of etching porous silicon with an aqueous NaOH solution (G. Bonchil, R. Herino, K. Barla, and J. C. Pfister, J. Electrochem. Soc., Vol. 130, No. 7, 1611 (1983)).
(2-3-2) The method of etching porous silicon with an etching solution which is capable of etching monocrystalline silicon.
In the above method (2-3-2), a fluoronitric-acid-type etching solution is generally used, and etching of silicon proceeds as follows: EQU Si+2O.fwdarw.SiO.sub.2 ( 10) EQU SiO.sub.2 +4HF.fwdarw.SiF.sub.4 +H.sub.2 O (11)
As shown by the above reaction formulas, Si is oxidized to SiO.sub.2, and the resultant SiO.sub.2 is etched with hydrofluoric acid, thus Si is etched.
In addition to the etchant for silicon crystal described above, other etchants are known such as ethylenediamine-type, KOH-type and hydrazine-type.
The etching solutions according to the above method (2-3-2) etch the crystalline silicon as well as porous silicon. Therefore, to accomplish the selective etching of the porous silicon, it is required to select etching solution capable of etching the porous silicon other than those for crystalline silicon described above. Thus, only aqueous NaOH solution has been used for selective etching of the porous silicon.
However, in the conventional method of selectively etching porous silicon with an aqueous NaOH solution, Na ions are inevitably adsorbed on the etched surface. The Na ions cause the primary impurity contamination which results in the interfacial states. Thus, Na ions must not be avoided to be introduced into the semiconductor process.
Moreover, as discussed above, the method (2-3) has significant problems that the size of n-type monocrystalline silicon is limited to 10.times.10 .mu.m.quadrature. (G. Bomchil and A. Halimaoui, "Porous Silicon: The material and its application to SOI technologies", Microelectronic Engineering, 8(1988), pp.293-310)), and the substrate is warped. In the view of these problems, inventors have developed a method for forming a monocrystalline silicon layer on an insulating material, achieving the great improvement of the conventional technologies typically including the method (2-3).
FIGS. 1A to 1D are schematic sectional views showing the processes for forming a monocrystalline silicon layer on an insulating material. A 200 .mu.m-thick p-type silicon substrate (not shown) is anodized with a current of current density of 100 mA/cm.sup.2 in a 50% hydrofluoric acid solution for 24 minutes, then all the portion of the p-type silicon substrate becomes porous, thus the porous silicon substrate 1 is obtained as shown in FIG. 1A. Next, an epitaxial layer 2 is grown on the porous silicon substrate 1.
After that, a quartz substrate 3 is prepared and the epitaxial layer 2 on the porous silicon substrate is bonded to this quartz substrate 3 as shown in FIG. 1B. Then, the bonded porous silicon substrate is removed, while the monocrystalline epitaxial layer 2 remains on the quartz substrate 3 as shown in FIG. 1C. Further, as shown in FIG. 1D, the epitaxial layer 2 is partially etched to be divided into the isolated elements, that is, the epitaxial layer 2 is divided into the epitaxial layers 2a-2c.
Unfortunately, the method for forming a monocrystalline silicon layer on an insulating material described above has the problem that it takes long time to perform the process of forming the porous silicon substrate 1 because the whole p-type silicon substrate is required to be converted into the porous material. This is one of problems to be improved.
Another problem to be solved is its high cost due to the fact that a p-type silicon substrate can be used only once because the whole p-type silicon substrate must be etched away after being anodized into a porous material.
In the technology of "SOI with a bonded substrate", typically including the method (2-3), the process for thinning the silicon substrate is important. That is, it is required to thin a silicon substrate having large thickness such as a few hundred microns to a very small thickness of a few microns or less than one micron with a very good uniformity in the resultant thickness by means of polishing or etching. This has significant technical difficulty in controllability and uniformity of the resultant thickness. Although, among various SOI technologies, this method can give the highest quality of a thin monocrystalline layer, this technology has not been in use for production because of its difficulty in controlling the thickness.
When an insulating material other than silicon is used for a substrate to support silicon layer, there is another important problem in the SOI with a bonded substrate that stress results from the difference in thermal expansion coefficient between the silicon layer and the insulating substrate supporting the silicon layer. Such a stress almost never occurs when a silicon substrate is used as a supporting substrate (that is, silicon is bonded to a silicon substrate), but when an insulating substrate other than silicon, such as a glass, is used as a supporting substrate, there occur some problems during the heat treatment at about 1000.degree. C. to increase the bonding strength after two substrates are bonded. For example, warpage or cracking might occur in the substrate with bonded two materials, or a substrate might come off the other substrate, due to the difference in thermal expansion coefficient between the two substrates. There are some examples attempting to synthesize a material having a thermal expansion coefficient near that of silicon for use as a supporting substrate, but, to our best knowledge, such materials do not have good heat-resistance and they can not endure high temperatures for the treatment to increase the bonding strength or for device fabrication processes. If the thickness of the silicon substrate is thinner, then there exist less possibility of warping or cracking in the substrate, or separation of the two substrates during heat treatment. However, even only 0.1 .mu.m-thick monocrystalline silicon film leads to warpage which is large enough to give some errors in photomask alignment after the heat treatment in the conventional semiconductor fabrication processes.